Liquid crystal display devices (LCDs) characterized by their thin design, light weight and low power consumption have come into widespread use in recent years and are utilized in the display units of mobile devices such as portable telephones (mobile telephones or cellular telephones), PDAs (Personal Digital Assistants) and laptop personal computers. Recently, however, liquid crystal display devices have come to be provided with large-size screens and techniques for dealing with moving pictures have become more advanced, thus making it possible to realize not only mobile applications but also stay-at-home large-screen display devices and large-screen liquid crystal televisions. Liquid crystal display devices that adopts an active matrix drive system and are capable of presenting a high-definition display are being utilized as these liquid crystal displays devices.
Referring first to FIGS. 34A and 34B, a typical configuration of a display of the active matrix driving system will be briefly described. Referring first to FIG. 34A, a display unit 960 of the display of the active matrix driving system comprises a semiconductor substrate on which pixel parts 950 are arranged in the form of a matrix and in which scan lines 961 and data lines 962 are arranged in the form of a grid. In the case of a color SXGA panel, for example, the matrix is composed of 1280×3 pixel columns and 1024 pixel rows. The scan lines 961 and the data lines 962 are connected to a gate driver 970 and to a data driver 980, respectively. The gate driver 970 sends a scan signal to a pixel 950 via a scan line 961, while the data driver 980 sends a gray scale voltage signal, matched to video data, to the pixel 950 via a data line 962. Further, the gate driver 970 and data driver 980 are controlled by a display controller not shown, a required clock CLK, control signals and power-supply voltage, etc., are supplied from the display controller, and video data is supplied from the display controller to the data driver 980. At the present time, video is principally digital data.
In FIG. 34B, the essential portions of the pixel part 950 (for one pixel) in a liquid crystal display are schematically shown by an equivalent circuit. Thus, the pixel part 950 includes a TFT (thin-film transistor) 951, a pixel electrode 952, a liquid crystal (capacitance) 953, and a common electrode 954. The TFT 951 is connected, as a switching device, between the data line 962 and the pixel electrode 952, and has its control end connected to the scan line 961. As for the liquid crystal (capacitance) 953, the liquid crystal, sandwiched between the pixel electrode 952 and the common electrode 954, operates as a capacitance element. The common electrode 954 is formed as a sole transparent electrode on an entire major surface of an opposing substrate, mounted facing the semiconductor substrate. The liquid crystal is sealed in a space between the semiconductor substrate and the opposing substrate.
The scheme for display is briefly as follows: The TFT 951, having the switching function, is on and off controlled by the scan signal. When the TFT 951 is turned on, a gray-scale voltage signal, corresponding to a video data signal, is supplied to the pixel electrode 952. The liquid crystal is varied in its light transmittance by the potential difference between the pixel electrode 952 and the common electrode 954. This potential difference is kept for a preset time period by the liquid crystal (capacitance) 953, to display the image, even after turning off the TFT 951. Meanwhile, a holding capacitor or the like may be provided between the pixel electrode 952 and the common electrode 954 for maintaining the potential in stability.
Rewriting of one screen of data is carried out over one frame ( 1/60 of a second), every pixel row (every line) is selected sequentially (TFT is sequentially turned on) by each scan line, and a grayscale signal voltage is supplied from each data line within the selection interval.
There is marked interconnection capacitance in the scan line 961 and the data line 962, due to the interconnection resistance proper to the lines, capacitance generated in the intersections, and to the capacitance of the liquid crystal sandwiched between the semiconductor substrate and the counter substrate. Hence, a high driving capability is required of the gate driver 970 and the data driver 980. It is noted that the larger the display size and/or the higher the resolution, the higher is the driving capability needed.
It is sufficient that the gate driver 970 supplies at least binary-scan signals. It is however required of the data driver 980 to drive the data line with a multi-valued gray scale voltage signal corresponding to the number of gray scale levels. Hence, the data driver 980 includes a decoder for converting video data into gray-scale voltage signal, and a digital-to-analog converter (DAC) for amplifying the gray-scale voltage signal and for outputting the so amplified voltage signal to the data line 962.
In color liquid crystal display devices, the number of gray scale levels to be displayed has increased in recent years. Specifically, there is a strong demand for at least 260 thousand colors, with use of six bit video data for each of R, G and B, and even for 26 million and 800 thousand colors, with use of eight bit video data for each of R, G and B.
For this reason, a data driver, outputting gray-scale voltage signal, corresponding to multi-bit video data, is required to output the voltage with extremely high accuracy. On the other hand, the number of devices of the circuit part, processing the video data, and hence the chip area of a data driver LSI, have increased, thus raising the cost.
The configuration in which the chip area of the data driver LSI is suppressed from increasing, despite the use of larger numbers of bits, is disclosed in Patent Document 1, recited below. FIG. 35 hereof corresponds to FIG. 16 of the Patent Document 1, and shows an exemplary configuration of a data driver proposed in the Patent Document 1. Referring to FIG. 35, this data driver includes a latch address selector 981, a latch 982, a gray-scale voltage generator 986, a decoder 987 and an amplifier circuit 988.
The latch address selector 981 decides on the data latching timing, based on a clock signal CLK.
The latch 982 latches digital video data, based on the timing, as determined by the latch address selector 981, and unanimously outputs data to the decoders 987, responsive to an STB signal (strobe signal).
The gray-scale voltage generator 986 generates gray-scale voltages, every two gray scale levels, thereby decreasing the total number of the gray-scale voltage lines of the decoder 987 to approximately one-half of that used conventionally, more specifically, used at the time of filing of the Patent Document 1, recited below.
The decoder 987 selects two gray-scale voltages, responsive to the video data, to output the so selected voltages to the amplifier circuit 988.
The amplifier circuit 988 is able to amplify and output two input gray-scale voltages and a gray-scale voltage which is intermediate between the two gray-scale voltages.
The configuration shown in the Patent Document 1, recited below, is provided with the amplifier circuit 988 which is supplied with two gray-scale voltages to amplify one of the two gray-scale voltages and the intermediate voltage. With this configuration, the number of the gray scale voltage lines of the decoder 987 may be halved to reduce the circuit size of the decoder 987, thereby saving the circuit area and reducing the cost. The result is that the chip area of the data driver LSI may be suppressed from increasing, in order to cope with increase in the number of bits in the video data signals.
As an amplifier, suited for use as an amplifier circuit 988, the configuration shown in FIG. 5(b) of Patent Document 1, recited below, has been proposed. The configuration of FIG. 5(b) of Patent Document 1, in which an output of the differential pair is an input end of a diode-connected current mirror, is thought not to be operating as a differential amplifier. According to analyses by the present inventor, the amplifier circuit 988 may be an amplifier shown at 85-1 of FIG. 15 of Patent Document 3, recited below, although the two differ as to polarity types of the transistors.
On the other hand, the Patent Document 2, recited below, discloses the configuration for realization of the output voltage of the data driver of high accuracy, in order to cope with increase in the number of bits in the video data. In this Patent Document 2, showing a method for driving a liquid crystal display, a video signal voltage plus an offset voltage, and a video signal voltage minus the offset voltage, are alternately output from an amplifier circuit, at preset cycles, to a video signal line (data line), thereby balancing out the increase and the decrease of the luminance of the liquid crystal display caused by such offset.
As an amplifier circuit for implementing the driving method, the Patent Document 2, recited below, discloses an embodiment of a voltage follower circuit. However, area saving cannot be achieved in the amplifier circuit of the voltage follower configuration.
There is proposed in Patent Document 3, recited below, a configuration for implementing the driving method of Patent Document 2 by an amplifier circuit, which receives two gray-scale voltages to output one of the two gray-scale voltages and an intermediate voltage, as proposed in Patent Document 1, recited below.
FIG. 36 shows the configuration of an amplifier circuit of an output unit of the data driver, as proposed in Patent Document 3, recited below. This configuration corresponds to the configuration shown in FIG. 15 of Patent Document 3, recited below. Referring to FIG. 36, this amplifier circuit includes an amplifier 85-1 and a switch circuit 42. In the amplifier 85-1, transistors Q14 and Q13, which constitutes a second differential pair, are connected in parallel with transistors Q11 and Q12, which have sources connected in common, and which constitutes a first differential pair. The first and second differential pairs are driven by a common current source Q1. A current mirror (Q3, Q4) is connected in common, as a load circuit, to output pairs of the first and second differential pairs. The point of common connection of an output end of the current mirror (Q3, Q4) (the drain of transistor Q4) and the transistors Q12 and Q13 is an output of the differential stage, which output is connected to the gate of a transistor amplifier Q5. The gates of the transistors Q12 and Q13 are non-inverting input ends, while the gates of the transistors Q11 and Q14 are inverting input ends. The gates of the transistors Q11 and Q14 of the amplifier 85-1 are connected to an output end OUT. When two gray-scale voltages are supplied to the gates of the transistors Q12 and Q13, an intermediate voltage between the two gray-scale voltages can be output at the output end OUT.
With the amplifier of the above configuration,                in case the two input gray-scale voltages are equal to each other, the output voltage is equal to the input gray-scale voltage and        in case the two input gray-scale voltages are different from each other, the output voltage is intermediate between the two input gray-scale voltages.        
That is, the amplifier shown in FIG. 36 is desirable as amplifier circuit 988 of FIG. 33. The amplifier shown in FIG. 36 has also been proposed in FIG. 5 of Patent Document 4 (differential amplifier having two differential pairs), recited below.
With the Patent Document 3, recited below, the connection with regards to the differential input ends of the amplifier 85-1, input terminals IN1 and IN2, receiving the first and second gray-scale voltages, and the output end OUT, is controlled by the switch circuit 42, and                a first state in which the gates of the transistors Q12 and Q13 are connected to IN1 and IN2, respectively, and the gates of the transistors Q11 and Q14 are connected to the output end OUT;        a second state in which the gates of the transistors Q12 and Q13 are connected to IN2 and IN1, respectively, and the gates of the transistors Q11 and Q14 are connected to the output end OUT;        a third state in which the gates of the transistors Q11 and Q14 are connected to IN1 and IN2, respectively, and the gates of the transistors Q12 and Q13 are connected to the output end OUT; and        a fourth state in which the gates of the transistors Q11 and Q14 are connected to IN2 and IN1, respectively, and the gates of the transistors Q12 and Q13 are connected to the output end OUT;are changed over at a predetermined terminal.        
It is stated that, by periodically changing over between these four states, output offsets ascribable to the threshold variations of the transistors making up the amplifier 85-1 may be time-averaged and thereby canceled.
However, it may be surmised that, in the third and fourth states, no desired voltages can be output correctly, because two gray-scale voltages are supplied to the inverting input ends. It may be surmised that, in FIG. 36, the output offset may be canceled to a certain extent in case of switching between the first and second states.
There is also proposed in Patent Document 5, recited below, a configuration higher in performance than the amplifier 85-1 of FIG. 36. The configuration disclosed in this Patent Document 5 is an improvement over the configuration of Patent Document 4, in particular an improvement in the performance of output voltage accuracy.
FIG. 38 shows the configuration of an amplifier having plural differential pairs, as proposed in the Patent Document 5. In FIG. 38, the number of the differential pairs is selected to be two for comparison to the case of the amplifier 85-1.
Referring to FIG. 38, this amplifier includes transistors Q1A and Q1B, as a second differentia pair, connected in parallel with transistors Q0A and Q0B, forming a first differential pair. The first and second differential pairs are driven by separate current sources Q10 and Q11, respectively. Output pairs of the first and second differential pairs are connected to a current mirror (QL1, QL2) as a load circuit. A differential amplifier 209 is connected between an output pair of the current mirror (QL1, QL2) and an output terminal 3. The output pair of the current mirror (QL1, QL2) is connected to an inverting input end (−) and a non-inverting end (+) of the differential amplifier 209. An output end of the differential amplifier 209 is connected to the output terminal. The gates of the transistors Q0B and Q1B are connected to the output terminal 3. Two gray-scale voltages IN1 and IN2 are supplied to the gates of the transistors Q0A and Q1A, respectively.
Similarly to the amplifier 85-1 of FIG. 36, the amplifier of FIG. 38 is able to output a voltage intermediate between the two input gray-scale voltages IN1 and IN2. The amplifier of FIG. 38 differs appreciably from the amplifier 85-1 of FIG. 36 in such respects that current sources for driving the two differential pairs are discretized, whereby the amplifier of FIG. 38 may be improved appreciably in output voltage accuracy.
It is noted that, in the amplifiers of FIGS. 36 and 38, amplifier stage components (the amplifier transistor Q5 of the amplifier 85-1 of FIG. 36 and the differential amplifier 209 of FIG. 38) are among a number of variations of different configurations which may be interchanged with each other.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2001-34234A (FIGS. 5 and 16)
[Patent Document 2]
JP Patent Kokai Publication No. JP-A-11-249623A
[Patent Document 3]
JP Patent Kokai Publication No. JP-P2001-343948A (FIG. 15)
[Patent Document 4]
U.S. Pat. No. 5,396,425 (FIG. 5)
[Patent Document 5]
U.S. Pat. No. 6,246,351B1 (FIG. 2)